EPF8636A

Product Summary

The EPF8636A belongs to FLEX family, which combines the benefits of both erasable programmable logic devices (EPLDs) and fieldprogrammable gate arrays (FPGAs). The FLEX 8000 device family is ideal for a variety of applications because it combines the fine-grained architecture and high register count characteristics of FPGAs with the high speed and predictable interconnect delays of EPLDs. Logic is implemented in LEs that include compact 4-input look-up tables (LUTs) and programmable registers. High performance is provided by a fast, continuous network of routing resources. FLEX 8000 devices provide a large number of storage elements for applications such as digital signal processing (DSP), wide-data-path manipulation, and data transformation. These devices are an excellent choice for bus interfaces, TTL integration, coprocessor functions, and high-speed controllers. The high-pin-count packages can integrate multiple 32-bit buses into a single device.

Parametrics

Absolute maximum ratings: (1)VCC, Supply voltage With respect to ground: –2.0 to 7.0 V; (2)VI, DC input voltage: –2.0 to 7.0 V; (3)IOUT, DC output current, per pin: –25 to 25 mA; (4)TSTG, Storage temperature at No bias: –65 to 150 ° C; (5)TAMB, Ambient temperature Under bias: –65 to 135 ° C; (6)TJ, Junction temperature: Ceramic packages, under bias: 150 ° C max; PQFP and RQFP, under bias: 135 ° C max.

Features

Features: (1)Low-cost, high-density, register-rich CMOS programmable logic device (PLD) family; (2)System-level features: In-circuit reconfigurability (ICR) via external Configuration; EPROM or intelligent controller; fully compliant with the peripheral component interconnect (PCI) standard; Built-in Joint-Test Action Group(JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 on selected devices; MultiVolt I/O interface enabling device core to run at 5.0 V, while I/O pins are compatible with 5.0-V and 3.3-V logic levels; Low power consumption (typical specification less than 0.5 mA in standby mode); (3)Flexible interconnect: FastTrack Interconnect continuous routing structure for fast, predictable interconnect delays; dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators; dedicated cascade chain that implements high-speed, high-fan-in logic functions; Tri-state emulation that implements internal tri-state nets; (4)Powerful I/O pins: Programmable output slew-rate control reduces switching noise; (5)Peripheral register for fast setup and clock-to-output delay.

Diagrams