HD6417750RBP240V

Product Summary

The HD6417750RBP240V is a 32-bit RISC (reduced instruction set computer) microprocessor with a SH-4 CPU core and features upward compatibility with SH-1, SH-2, and SH-3 microcomputers at the instruction set level. The HD6417750RBP240V includes an instruction cache, an operand cache with a choice of copy-back or write-through mode, and an MMU (memory management unit) with a 64-entry fully-associative unified TLB (translation lookaside buffer). The HD6417750RBP240V has an 8-Kbyte instruction cache and a 16-Kbyte data cache.

Parametrics

HD6417750RBP240V absolute maximum ratings: (1)I/O, PLL, RTC, CPG power supply voltage:–0.3V to 4.2V, –0.3V to 4.6V ; (2)Internal power supply voltage:–0.3V to 2.5V, –0.3V to 2.1V; (3)Input voltage:–0.3V to VDDQ +0.3V ; (4)Operating temperature:–20℃ to 75℃; (5)Storage temperature:–55℃ to 125℃.

Features

HD6417750RBP240V features: (1)Superscalar architecture (providing simultaneous execution of two instructions) including FPU ; (2)Instruction execution time: Maximum 2 instructions/cycle ; (3)Virtual address space: 4 Gbytes (448-Mbyte external memory space) ; (4)Space identifier ASIDs: 8 bits, 256 virtual address spaces ; (5)On-chip multiplier ; (6)Five-stage pipeline ; (7)Fixed 16-bit instruction length for improved code efficiency ; (8)Load-store architecture ; (9)Delayed branch instructions ; (10)Conditional execution ; (11)C-based instruction set ; (12)Sixteen 32-bit general registers (and eight 32-bit shadow registers) ; (13)Seven 32-bit control registers ; (14)Four 32-bit system registers ; (15)Renesas Technology original SuperH architecture ; (16)32-bit internal data bus ; (17)Superscalar architecture: Parallel execution of two instructions ; (18)External buses ; (19)On-chip floating-point coprocessor ; (20)Supports single-precision (32 bits) and double-precision (64 bits) ; (21)Supports IEEE754-compliant data types and exceptions ; (22)Two rounding modes: Round to Nearest and Round to Zero ; (23)Handling of denormalized numbers: Truncation to zero or interrupt generation for compliance with IEEE754.

Diagrams