CY37032P44-125AXC

Product Summary

The CY37032P44-125AXC CMOS CPLD provides a range of high-density programmable logic solutions with unparalleled system performance. The CY37032P44-125AXC is designed to bring the flexibility, ease of use, and performance of the 22V10 to high-density CPLDs. The architecture is based on a number of logic blocks that are connected by a Programmable Interconnect Matrix (PIM). Each logic block features its own product term array, product term allocator, and 16 macrocells. The PIM distributes signals from the logic block outputs and all input pins to the logic block inputs. The CY37032P44-125AXC is electrically erasable and In-System Reprogrammable (ISR), which simplifies both design and manufacturing flows, thereby reducing costs. The ISR feature provides the ability to reconfigure the devices without having design changes cause pinout or timing changes. The Cypress ISR function is implemented through a JTAG-compliant serial interface. Data is shifted in and out through the TDI and TDO pins, respectively. Because of the superior routability and simple timing model of the CY37032P44-125AXC, ISR allows users to change existing logic designs while simultaneously fixing pinout assignments and maintaining system performance.

Parametrics

CY37032P44-125AXC absolute maximum ratings: (1)Storage Temperature: –65℃ to +150℃; (2)Ambient Temperature with Power Applied: –55℃ to +125℃; (3)Supply Voltage to Ground Potential: –0.5V to +7.0V; (4)DC Voltage Applied to Outputs in High-Z State: –0.5V to +7.0V; (5)DC Input Voltage: –0.5V to +7.0V; (6)DC Program Voltage: 4.5 to 5.5V; (7)Current into Outputs: 16 mA; (8)Static Discharge Voltage: > 2001V; (9)Latch-up Current: > 200 mA.

Features

CY37032P44-125AXC features: (1)In-System Reprogrammable (ISR) CMOS CPLDs; (2)JTAG interface for reconfigurability; (3)Design changes do not cause pinout changes; (4)Design changes do not cause timing changes; (5)High density; (6)32 to 512 macrocells; (7)32 to 264 I/O pins; (8)Five dedicated inputs including four clock pins; (9)Simple timing model; (10)No fanout delays; (11)No expander delays; (12)No dedicated vs. I/O pin delays; (13)No additional delay through PIM; (14)No penalty for using full 16 product terms; (15)No delay for steering or sharing product terms; (16)3.3V and 5V versions; (17)PCI-compatible; (18)Programmable bus-hold capabilities on all I/Os; (19)Intelligent product term allocator provides:; (20)0 to 16 product terms to any macrocell; (21)Product term steering on an individual basis; (22)Product term sharing among local macrocells; (23)Flexible clocking; (24)Four synchronous clocks per device; (25)Product term clocking; (26)Clock polarity control per logic block; (27)Consistent package/pinout offering across all densities; (28)Simplifies design migration; (29)Same pinout for 3.3V and 5.0V devices; (30)44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP, BGA, and Fine-Pitch BGA packages; (31)Lead(Pb)-free packages available.

Diagrams